1. Field of the Invention
This invention relates to an electro-luminescence display (ELD), and more particularly to a driving circuit for driving electro-luminescence cells arranged on an electro-luminescence panel in a matrix type.
2. Description of the Related Art
Generally, an electro-luminescence (EL) panel converts an electrical signal into light energy to thereby display a picture corresponding to video signals (or image signals). Such an EL panel includes EL cells arranged at intersections between gate lines and data lines. Each of the EL cells responds to a pixel signal from the data line to generate a light corresponding to a magnitude of the pixel signal.
In order to stably apply a pixel signal to each EL cell, the EL panel has cell-driving circuits scanned sequentially line-by-line. Each of the EL cell-driving circuits responds to a control signal at the gate line to sample a pixel signal at the data line and then holds the sampled pixel signal during the next frame interval, to thereby stably apply the pixel signal to the EL cell.
As shown in FIG. 1, a conventional EL cell-driving circuit for carrying out such sampling and holding operations of a pixel signal includes a first PMOS thin film transistor (TET) MP1 connected between an EL cell ELC and a first node Ni. A gate of the first PMOS TFT MP1 is connected to a second node N2, and the EL cell ELC is also connected to ground. A second PMOS TFT MP2 is connected between the second node N2 and the EL cell ELC, and is connected at its gate to a gate line GL. A capacitor C1 is connected between the first and second nodes N1 and N2.
The capacitor C1 charges a voltage of a pixel signal when the pixel signal is applied from a data line DL and applies the charged pixel voltage to gate electrodes of the first PMOS TFT MP1. The first PMOS TET MP1 is turned on by the pixel voltage charged in the capacitor C1, thereby allowing a supply voltage VDD applied, via the first node Ni, from a voltage supply line VDDL to be supplied to the EL cell ELC.
At this time, the first PMOS TFT MP1 varies its channel width depending on a voltage level of the pixel signal to control a current amount applied to the EL cell ELC. Then, the EL cell ELC generates a light corresponding to the current amount applied from the first PMOS TFT MP1. The second PMOS TET MP2 responds to a gate signal GLS, as shown in FIG. 2, applied from the gate line GL to selectively connect the second node N2 to the EL cell ELC.
More specifically, the second PMOS TFT MP2 connects the second node N2 to the EL cell ELC at a time interval when the gate signal GLS is enabled at a low logic, thereby allowing the pixel signal to be charged in the capacitor C1. In other words, the second PMOS TFT MP2 forms a current path of the capacitor C1 at a time interval when the gate signal GLS at the gate line GL is enabled. The capacitor C1 charges the pixel signal in the enabling interval of the gate signal GLS, thereby allowing the gate electrode of the first PMOS TFT MP1 to have a lower voltage than the drain electrode by a voltage level of the charged pixel signal. Accordingly, a channel width of the first PMOS TFT MP1 is controlled in accordance with a voltage level of the pixel signal to determine a current amount flowing from the first node N1 into the EL cell ELC.
The conventional EL cell driving circuit further includes a third PMOS TFT MP3, connected between the data line DL and the first node N1, responding to a gate signal at the gate line GL, and a fourth PMOS TFT MP4, connected between the voltage supply line VDDL and the first node N1, responding to an inverted gate signal /GLS from a gate bar line /GL.
The third PMOS TFT MP3 is turned on at a time interval when a low logic of gate signal is applied from the gate line GL, thereby connecting the capacitor C1, coupled to the first node N1 and the source electrode of the first PMOS TFT MP1, to the data line DL. In other words, the third PMOS TFT MP3 responds to a low logic of gate signal GLS to send a pixel signal at the data line DL to the first node N1. to the data line DL. In other words, the third PMOS TFT M3 responds to a low logic of gate signal GLS to send a pixel signal at the data line DL to the first node N1.
As a result, the third PMOS TFT MP3 is turned on during a time interval when a gate signal at the gate line GL remains at a low logic, thereby charging a pixel signal into the capacitor C1 connected between the first and second nodes N1 and N2. The fourth PMOS TET MP4 is turned on in a time interval when a low logic of inverted gate signal /GLS from the gate bar line /GL is applied to the gate electrode thereof, thereby connecting the first node N1, to which the capacitor C1 and the source electrode of the first PMOS TFT MP1 are connected, to the voltage supply line VDDL.
At a time interval when the fourth PMOS TET MP4 has been turned on, a supply voltage VDD at the voltage supply line VDDL is applied, via the first node N1 and the first PMOS TFT MP1, to the EL cell ELC. Thus, the EL cell ELC generates a light of a quantity according to a voltage level of the pixel signal.
In the conventional EL cell driving circuit, a maximum current amount (i.e., a current margin of a pixel signal) required for obtaining a maximum brightness is small. For this reason, a current difference between gray scale levels of a video signal is approximately several μA. if a current difference between gray scale levels is set to several μA, a data driver integrated circuit (IC) chip must have the ability to control current at a range of several μA accurately. However, it is very difficult to manufacture a data driver IC chip capable of controlling a current at a range of several μA accurately. As a result, the conventional EL cell driving circuit has problems with driving the conventional EL panel to accurately display a gray scale of a picture.